| MINIUART Project Status | |||
| Project File: | miniuart.ise | Current State: | Programming File Generated |
| Module Name: | Interface |
|
No Errors |
| Target Device: | xc2vp30-7ff896 |
|
28 Warnings |
| Product Version: | ISE 9.1.03i |
|
Thu Nov 29 22:35:51 2007 |
| MINIUART Partition Summary | |||
| No partition information was found. |
| Device Utilization Summary | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slice Flip Flops | 137 | 27,392 | 1% | |
| Number of 4 input LUTs | 338 | 27,392 | 1% | |
| Logic Distribution | ||||
| Number of occupied Slices | 224 | 13,696 | 1% | |
| Number of Slices containing only related logic | 224 | 224 | 100% | |
| Number of Slices containing unrelated logic | 0 | 224 | 0% | |
| Total Number of 4 input LUTs | 370 | 27,392 | 1% | |
| Number used as logic | 338 | |||
| Number used as a route-thru | 32 | |||
| Number of bonded IOBs | 4 | 556 | 1% | |
| IOB Flip Flops | 1 | |||
| Number of PPC405s | 0 | 2 | 0% | |
| Number of GCLKs | 1 | 16 | 6% | |
| Number of GTs | 0 | 8 | 0% | |
| Number of GT10s | 0 | 0 | 0% | |
| Total equivalent gate count for design | 3,477 | |||
| Additional JTAG gate count for IOBs | 192 | |||
| Performance Summary | |||
| Final Timing Score: | 0 | Pinout Data: | Pinout Report |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report |
| Timing Constraints: | All Constraints Met | ||
| Detailed Reports | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos |
| Synthesis Report | Current | Thu Nov 29 22:34:51 2007 | 0 | 27 Warnings | 2 Infos |
| Translation Report | Current | Thu Nov 29 22:35:00 2007 | 0 | 0 | 0 |
| Map Report | Current | Thu Nov 29 22:35:08 2007 | 0 | 0 | 3 Infos |
| Place and Route Report | Current | Thu Nov 29 22:35:32 2007 | 0 | 1 Warning | 2 Infos |
| Static Timing Report | Current | Thu Nov 29 22:35:36 2007 | 0 | 0 | 3 Infos |
| Bitgen Report | Current | Thu Nov 29 22:35:51 2007 | 0 | 0 | 0 |